1. Field of the Invention
The present invention relates to a semiconductor memory device; more particularly, to a system and method for maintaining data coherency in synchronous pipeline type semiconductor memory devices.
2. Description of the Related Art
Synchronous pipeline type semiconductor memory devices generally use a common input output (IO) mode in which input/output signal busses are shared to reduce package complexity, cost of chip, and ease of system mount on board, etc. However, such a common IO mode may cause a data contention problem between output data being outputted from memory cells and input data that are recorded in memory cells in a back-to-back operation such as a write-to-read operation or a read-to-write operation.
Therefore, to prevent the data contention problem, a dead cycle, that is, a no-operation period (NOP) should be added while a read operation is changed to a write operation. For this reason, many synchronous pipeline type semiconductor memory devices tend to employ the late write mode during write operations in which input data is input about 1 cycle to 2 cycles later than input addresses, thereby minimizing the number of NOP cycles.
Conventional synchronous type semiconductor memory devices for high-speed operation are disclosed, for example, in U.S. Pat. No. 5,717,653 to Suzuki, issued on Feb. 10, 1998, xe2x80x9cLate-write type SRAM in which address decoding time for reading data differs from address-decoding time for writing data.xe2x80x9d Suzuki describes a late-write type SRAM wherein the total time required to write data can be reduced.
The late-write type memory device in a late write operation delays write addresses inputted from the outside for several cycles to input the write address to an address decoder and select word lines and bit lines. A data input signal inputted from the outside after being delayed by several cycles from write address input is transmitted to a write driver, thereby a write operation starts after several cycles. That is, the write operation after 2 cycles in a late-write type memory device means that data to be written is input 2 cycles after a write address is input.
In such a late write method, when a write operation is changed into a read operation, data inputted in a final write operation are not written in a predetermined memory cell in a cell array, but stored in an input register only. Accordingly, if a read operation for an address corresponding to the final write operation is performed, the semiconductor memory device directly transmits data in an input register, not in a memory cell, to an output driver. This is called a bypass operation.
Recent semiconductor memory devices employ the bypass operation to maintain data coherency other than the late write mode. That is, in such semiconductor memory devices, when write order is input several cycles before read order is input and a write address is the same as a read address, a prior write data is output through an output buffer without a normal read operation from a memory cell.
FIG. 1 shows a conventional circuit block performing a bypass operation to maintain data coherency in a synchronous type semiconductor memory device. Where the address SAx register 10 samples and stores an external address SAx every cycle according to the internal clock signal KAI. The stored external address SAx is output as an input address RSAx. The input address RSAx is output as a read address signal ADDRESS T through the multiplexer 14 responding to the internal clock KAR in a read operation, and stored in the write address register 12 responding to the internal clock KAW in a write operation. The input address stored in the write address register 12 is output as a write address WSAx, and output as a write address signal ADDRESS C through the multiplexer 14 responding to the internal clock KAW in a next write operation. The read address signal ADDRESS T and write address signal ADDRESS C are input to column and row address decoders (not shown).
A comparator 16 compares the input address RSAx with the write address WSAx to determine whether the write address is the same as the input address. Here, the input address RSAx is a read address in a late write mode. Bypass comparison signals BYP1_SAx being outputted from the comparator 16 is input to a bypass summator 17. The bypass summator 17 sums the bypass comparison signals BYP1_SAx to output a summation signal BYPSUMB to a bypass control part 24. The bypass control part 24 receives and logically gates the bypass summation signal BYPSUMB and the internal clock signal KFLAG to output a bypass control signal KBYP and a core control signal KCORE. When the bypass control signal KBYP is enabled, the core control signal KCORE is disabled, thereby stopping an operation in a first transmission part 22. Accordingly, the output data of a sense amplifier amplifying data in a memory cell in a memory array cannot be transferred to a data output buffer 30. On the other hand, when a second transmission part 28 is operated, the write data WDIN that has not been stored in the memory cell but stored in a data input register 26 is input to the data output buffer 30. That is, the bypass operation is performed. The data output buffer 30 outputs the write data WDIN to the off-chip driver OCD 32 in response to the buffer control signal KDATA. The off chip driver 32 drives and finally outputs the buffered write data WDIN as an external output data XDQ.
However, it is difficult to apply the data coherency maintaining circuit in FIG. 1 to late selection synchronous pipeline type semiconductor memory devices in which two or more memory banks or chips are incorporated into a single chip. The late selection synchronous pipeline memory has, for example as shown in FIG. 2, two cache memory chips 2, 4 combined in one chip and a multiplexer 6 for selecting one of the outputs of the cache memory chips 2, 4 in response to the selection signal SAS. It is difficult to realize a bypass operation by applying the data coherency maintaining circuit shown in FIG. 1 to the late selection synchronous pipeline type memory device in FIG. 2. The reason is that the conventional data coherency maintaining circuit in FIG. 1 is designed to perform the bypass operation for a single bank or memory chip.
The reason why the late selection synchronous pipeline memory devices as shown in FIG. 2 employ the scheme in which two separate memory chips are combined into a single chip is to reduce the board area in the system or the loading burden. The semiconductor memory device having the scheme as shown in FIG. 2 is designed to perform the late write operation in the timing view as shown in FIG. 3. It is desired that the data coherency maintaining method or the structure in the data coherency maintaining circuit is improved to be applicable to the late selection synchronous pipeline type memory devices.
As described, the conventional data coherency maintaining circuit is suitable for a single memory chip, but not for a semiconductor memory device of the late select synchronous pipeline type. Accordingly, a need exists for a data coherency maintaining method and system which is suitable for a semiconductor memory device having the scheme in which two or more memory banks or chips are packaged into one chip.
Accordingly, it is an object of the present invention to provide a late write type semiconductor memory device by which the aforementioned problems are solved.
It is another object of the present invention to provide a semiconductor memory device having a data coherency maintaining circuit that is appropriate for a semiconductor memory device having a scheme in which at least two memory banks or chips are packaged in a single chip.
It is still another object to provide a data coherency maintaining method and circuit which is appropriate to a late select synchronous pipeline type semiconductor memory device that is operated by a late select synchronous pipeline type input/output protocol and has at least two memory chips in which each of separate read paths is connected to a common input/output port.
It is still another object to provide a static random access memory with which data access operation is performed with various bypass operation in late select synchronous pipeline type semiconductor devices operating at high speed.
To accomplish the aforementioned and other objects, the present invention provides a method of maintaining data coherency in a semiconductor memory device that is operated according to a late select synchronous pipeline type input/output protocol and has at least two memory chip blocks each of which has a read path connected to a common input/output port. The method of maintaining data coherency includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the at least two memory chip blocks and a normal read operation is performed through other read paths when all of the comparison signals are same.
According to another aspect of the present invention, there is provided a data coherency maintaining circuit for a semiconductor memory device that is operated according to a late select synchronous pipeline type input/output protocol and has at least first and second memory chip blocks each of which has a read path connected to a common input/output port. The data coherency maintaining circuit includes a bypass summator for generating first and second bypass summation signals by utilizing a chip block select address signal and comparison signals obtained from comparison between a write address inputted in a latest write operation and a current read address; a bypass control part for generating first and second bypass control signals and first and second core control signals having logic values contrary to logic values of the first and second bypass signals, respectively, by utilizing the first and second bypass summation signals and an internal clock signal; a first switching part for shutting off a read path of the first memory chip block in response to a disable state of the first core control signal and bypassing write data stored in a data input register to a data output buffer in response to an enable state of the first bypass control signal; and a second switching part being operated contrary to an operation of the first switching part in a bypass operation such as transferring output data that is read from the second memory chip block to the data output buffer in response to an enable state of the second core control signal and preventing bypass of the write data stored in the data input register in response to a disable state of the second bypass control signal.
The present invention has advantages such that a bypass operation for maintaining data coherency is effectively performed in a semiconductor memory device having a scheme in which two or more banks or memory chips are combined into one chip.